After spending most of the day at the beach, some more experimentation – with a fractional-N approach. Two little chips were around from another project, why not give it a try:

(1) The Analog Devices ADF4157, 6 GHz, 25 bit fixed modulus fractional-N PLL – this part is really great, for many purposes. It’s more or less pure magic what these folks at Analog do and achieve.

(2) To make it work up to 18 GHz, a prescaler is needed. Well, unfortunatly, I only have a :8 prescaler (ADF5002) around – this will give 0.25 to 2.25 GHz, for the 2 to 18 GHz input. Not quite ideal, because at 2 GHz it’s getting really into low frequencies for the ADF4157, and the output power of the ADF5002, which is a more-than-sufficient -5 dBm in the 4 to 18 GHz, range, but dropping off to only about -10 dBm at 2 GHz. At the same time, RF input sensitivity of the ADF4157 drops considerably for input frequencies below 0.5 GHz… we will see.

Some calculations:
With a 10 MHz reference clock, and the phase detector frequency set to 1.25 MHz (reference divider=8), this will result in 10 MHz steps, with 2^25 spacings in between. This gives about 0.298 Hz resolution. And moreover, with this setting, 10 MHz steps are possible, with no fractional-N divisor (which can always lead so some rather unpredictable fractional-N spurs).

The circuit – there is no big secret to it, a 5k1 reference resistor to set the charge pump current to 5 mA, and a few 6k8 resistors (0805 SMD) to make the chip compatible to a 5 V digital world. Two SMA connectors – one for the signal, and one for the 10 MHz reference. All wiring is done with 0.08 mm tinned copper wire… hope you have a steady hand. With a drop of epoxy glue, everything is held in place and well-protected.

Tests will follow – currently the loop bandwidth tests are running for the 1295, with the ADF41020 PLL.